1. Field of the Invention
The present invention relates to a semiconductor device and a data processing system, and, more particularly relates to a semiconductor device and a data processing system to which at least one portion of all bits of control information (for example, information about a command, an address, or the like) used for data communication is serially transferred.
2. Description of Related Art
As a representative type of this kind of semiconductor devices, synchronous semiconductor memory (memory device) is well known. Such a semiconductor memory serially receives a command or control information as address information from an external device such as a controller and a CPU, serially returns data to the external device in a data read operation, and receives data serially sent from an external device in a data write operation.
Meanwhile, data transfer speed is becoming increasingly faster in the recent years, and along with the trend, the speed of a tester that checks operations of a semiconductor memory needs to be accelerated. However, the operation speed of testers has not been as good as that of semiconductor memories, and even if they are provided with a faster operation speed, the cost will be very expensive.
Japanese Patent Application Laid-open No. 2006-277872 (hereinafter called “patent document 1”) discloses a technique in which a test using a low-speed tester is performed on a synchronous semiconductor memory that performs a high-speed data transfer.
By the technique disclosed in the patent document 1, data to be communicated at a speed corresponding to an internal clock speed of a semiconductor memory (that is, a data transfer speed inside the semiconductor memory) can be supplied and received by a tester operated at a lower speed than the speed of the semiconductor memory.
As a development of the synchronous semiconductor memory, there has been proposed a multiport semiconductor memory including a plurality of ports, to and from which data can be independently read and written. In such a semiconductor memory, as disclosed in “Architectural Considerations for Next-Generation Memory Systems (Rambus Develop Forum, Nov. 28, 2007)” (hereinafter called “non-patent document 1”), specifications in which a transfer speed of control information of a command/address system is accelerated as fast as a data transfer speed are considered.
However, the patent document 1 is not at all concerned with a case that the information transfer speed of the command/address system is accelerated as fast as the data transfer speed, as described in the non-patent document 1. Further, the technique disclosed in the patent document 1 cannot deal with the acceleration of the data transfer speed in practice.